In a potentially transformative development for the global semiconductor industry, artificial intelligence powerhouse NVIDIA is projected to integrate Intel’s advanced Foveros chip packaging technology into its backend manufacturing processes starting in the second half of 2028.
The forecast, detailed in a comprehensive research report by Jeff Pu, an industry analyst at South Korea-based GF Securities, points to a major strategic realignment in how the world’s most advanced AI hardware is manufactured. As the demand for high-performance computing and artificial intelligence accelerators continues to surge, the semiconductor supply chain has faced unprecedented pressure. NVIDIA’s rumored move to diversify its packaging partners represents a critical step toward mitigating supply chain vulnerabilities, reducing its singular dependence on Taiwan Semiconductor Manufacturing Company (TSMC), and leveraging Intel’s growing capabilities as a leading-edge contract foundry.
For years, TSMC has served as the primary manufacturing and packaging partner for NVIDIA’s market-dominating AI GPUs, including the Hopper and Blackwell architectures. However, the sheer volume of demand has routinely pushed TSMC’s advanced packaging facilities to their absolute limits, creating persistent supply bottlenecks for enterprise customers waiting on AI hardware. By eyeing Intel’s advanced packaging ecosystem, NVIDIA is positioning itself to secure a highly reliable secondary source of supply, which could stabilize the global market for AI chips and ensure more consistent delivery timelines.
The timing of this projected partnership is particularly noteworthy. The transition is expected to align with the commercial readiness of Intel’s highly anticipated 14A (1.4-nanometer class) production node. This synchronization suggests that by 2028, Intel will not only have refined its next-generation transistor fabrication capabilities but will also have scaled its advanced packaging infrastructure to a level capable of meeting the stringent quality and volume demands of a client as massive as NVIDIA.
Backend Technologies Gain Prominence in Semiconductor Manufacturing
To understand the significance of NVIDIA’s potential shift, it is essential to look at how modern semiconductor manufacturing is structured. The production of cutting-edge silicon, particularly complex processors like AI GPUs, is divided into two primary phases: frontend and backend manufacturing.
The frontend process involves wafer fabrication, where advanced lithography machines print billions of microscopic transistors onto silicon wafers. This phase determines the raw logic, processing power, and architectural foundation of the chip. Historically, the industry focused almost entirely on frontend advancements to drive performance, a trend dictated by Moore’s Law. However, as physical limitations make it increasingly difficult and expensive to shrink transistors further, the industry has shifted its focus to the backend.
The backend process, which encompasses advanced packaging, has emerged as the new frontier of semiconductor innovation. Once the silicon dies are fabricated on the wafer, they must be cut, arranged, interconnected, and enclosed in a protective housing that allows them to communicate with the rest of the system—such as high-bandwidth memory (HBM) and system boards. In the era of AI, where processors require massive memory bandwidth and ultra-low latency, packaging is no longer just a protective shell; it is a critical determinant of system performance.
While Intel continues to compete fiercely with TSMC in frontend manufacturing, the American chipmaker has made a strategic decision to aggressively market its advanced backend packaging services to third-party clients. This approach allows rival chip designers to utilize Intel’s packaging technologies even if they choose to manufacture their primary silicon dies at other foundries like TSMC.
This open foundry strategy has already begun to yield significant dividends for Intel. Previous industry reports indicated that Google selected Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and EMIB-T technologies for its custom Tensor Processing Unit (TPU) chips. This adoption by a major hyperscaler served as an early proof of concept for Intel Foundry Services (IFS), proving that the company’s backend technologies are highly competitive and viable for enterprise-grade AI hardware. Jeff Pu’s latest analysis suggests that NVIDIA is prepared to follow a similar path, further validating Intel’s role as a vital pillar of the global semiconductor supply chain rather than just an integrated device manufacturer.
The Architectural Advantages of Foveros 3D Stacking
At the heart of NVIDIA’s projected shift is Intel’s proprietary Foveros technology, which represents a major leap forward from traditional packaging methodologies. To appreciate the benefits Foveros brings to high-performance AI chips, it is helpful to compare it to existing 2.5D packaging solutions like Intel’s own EMIB.
Traditional 2.5D packaging, such as EMIB, relies on placing multiple silicon dies side-by-side on a horizontal plane, using a silicon bridge embedded in the substrate to facilitate high-speed communication between them. While highly effective for many applications, horizontal placement inherently limits how close components can be positioned. As the physical footprint of the chip package expands, it occupies more space on the server motherboard and requires longer interconnect paths, which can introduce latency and increase power consumption.
In contrast, Foveros is a true three-dimensional (3D) face-to-face die-stacking technology. Instead of arranging chips side-by-side, Foveros allows engineers to stack compute, memory, and specialized logic layers vertically, directly on top of a base die (often referred to as the active substrate). This base die handles power delivery and basic input/output (I/O) functions, while the high-performance logic and memory layers sit directly above it.
This vertical integration offers several key advantages for next-generation AI processors:
- Minimized Physical Footprint: By stacking components vertically, Foveros drastically reduces the overall surface area of the chip package. This compact design is highly beneficial for modern data centers, where space is at a premium and hardware density is directly tied to operational efficiency.
- Massive Bandwidth and Low Latency: Stacking dies vertically shortens the physical distance that electrical signals must travel between the processing cores and memory layers. Shorter distances translate directly to faster communication speeds, reduced signal degradation, and significantly lower latency.
- Superior Energy Efficiency: Moving data horizontally across a substrate requires a relatively high amount of power. By utilizing vertical through-silicon vias (TSVs) to connect stacked dies, Foveros minimizes the energy required to transmit data between layers, resulting in a much more power-efficient processor.
For NVIDIA, whose future AI roadmaps will undoubtedly demand unprecedented levels of memory bandwidth and energy efficiency to train increasingly complex large language models, the architectural benefits of Foveros 3D stacking are highly compelling.
A Strategic Balance for the Global Tech Ecosystem
Should the projections materialize, NVIDIA’s adoption of Intel’s Foveros packaging in 2028 will have far-reaching implications for the broader technology sector. For Intel, securing NVIDIA as a major backend customer would represent a crowning achievement for its foundry turnaround strategy, demonstrating that its packaging technologies can attract even its direct competitors in the AI space. It would provide Intel with a highly lucrative, steady stream of revenue to offset the massive capital expenditures required to build and maintain modern fabrication facilities.
For NVIDIA, the move represents a calculated risk-management strategy. Over-reliance on a single foundry partner has long been viewed as a systemic vulnerability for the company, particularly given the geopolitical complexities surrounding Taiwan, where TSMC’s primary advanced packaging facilities are located. By integrating Intel’s US- and global-based packaging facilities into its supply chain, NVIDIA can establish a more geographically diversified manufacturing footprint, protecting its operations from localized supply disruptions.
Ultimately, this partnership could serve as a vital stabilizing force for the global tech economy. By introducing a formidable alternative in the advanced packaging market, the collaboration between NVIDIA and Intel has the potential to alleviate the persistent hardware shortages that have characterized the early years of the AI boom, fostering a more competitive, resilient, and dynamic semiconductor landscape.
